We can support your Company to overcome all the Signal-Integrity issues that you could face in the course of your project(s). By working closely together with your design and PCB-layout engineers we will give you all the necessary support at all stages of the development process.
Below is a list of some of the tasks that we can undertake for you:
Stack Up Definition (pre-layout)
Defining the most appropriate PCB stack-up is one of the most important tasks and can be particularly complex due to the fact that it is often necessary to compromise between: costs, routing space and signal and power integrity requirements. At this stage, it is also important to have a clear idea of which kinds of PCB technology are required in terms of: minimum width and clearance of the traces, vias technology (HDI, traditional, etc.) and materials.
Signal Termination (pre-layout)
According to the maximum expected traces’ length and drivers’ characteristics, it is necessary to evaluate whether or not the signals require termination. Complex termination topology can also be evaluated (e.g. DDRx memories and buses).
Drivers' performance (pre-layout)
It could be necessary to evaluate the drivers’ performance using the real load and different working conditions (corners) in order to be able to determine whether, for example, a buffer needs to be added.
Determination of hi-speed geometrical routing rules (pre-layout)
- minimum trace-to-trace clearance for same and other signals’ groups
- maximum parallel/tandem distances
- buses’ routing topology
- maximum traces’ length
- trace length matching and tolerance
- terminations’ physical position
- maximum number of vias allowed
- routing layers
Hi-speed differential signals (pre- and post-layout)
S-parameters analysis for hi-speed differential channels (serdes) is a powerful tool that allows us to predict with great accuracy the potential problems could be encountered due to inappropriate: layout, stack-up, connectors, materials and vias’ dimension and placement.
Power-Integrity (pre- and post-layout)
It is possible to predict or verify whether the PDS’ impedance is “low-enough” to satisfy the maximum IC’s ripple voltage.
The impedance of the PDS is a result of the contribution of all its parts and therefore each part needs to be carefully considered during the analysis. For example, decoupling capacitors contribute to keeping the PDS’ impedance “low-enough” from 1 to 100 Mhz (or more). But this only works if the capacitor’s connections (traces and vias) to the PCB have a “low enough” inductance. With software simulations, it is possible to verify whether all the PDS’ components have been properly placed and routed.
We are also able to evaluate whether the power rails present excessive drop-voltage due to copper bottle-necks in the power planes. (IR).
DDRx memories (post-layout)
Once routed, we are able to test and tune the DDRx circuit. By driving, from the controller side, all the signals it is possible to verify the correct functionality of the memories. Usually, the test is carried out by generating stimulations compatible with JEDEC standards.
SI batch verification (post-layout)
Once the PCB is partially or completely routed, it is possible to verify quickly the most critical nets, evaluating: excessive ringing, cross-talks, and delays.
Usually routing a PCB with a Signal-Integrity approach requires an advance PCB CAD that is able to support complex rules and routing topology. If you don’t have the right software tools, we can also provide a full PCB layout service for you.
If you require further information please do not hesitate to contact us.
